1. Field of the Invention
This invention relates to a process of fabricating metal interconnects, and more particularly, to a self-aligned via process designed to prevent via poisoning
2. Description of Related Art
As the integration of an integrated circuit (IC) device is increased, a semiconductor wafer is less able to provide enough surface space for placing needed interconnects. Therefore a design containing more than two metal layers has been applied to fabricating the interconnects of a downsized metal oxide semiconductor (MOS) transistor. In the design of such a semiconductor device, an inter-metal dielectric (IMD) layer is normally placed between metal layers to prevent unnecessary connections. Furthermore, the degree of planarity of an IMD layer affects the difficulty of the follow-up deposition and etching processes of a metal layer, and the resolution of a photolithography process as well.
Because hydrogen silsesquioxane (HSQ), a spin-on-glass (SOG), has low-permittivity, carbon-free, and reflowable, HSQ has recently been used in the semiconductor fabrication process to prevent pollution during an etching back process. HSQ also has a high gap filling capability, so using HSQ reduces processing steps and lowers production cost. Furthermore, bonding between silicon and hydrogen (Si--H) in the HSQ prevents the HSQ layer from absorbing moisture, so that HSQ is used as the direct-on-metal dielectric for a better planarity and a lower parasitic capacitance. In addition, using a HSQ dielectric layer in a semiconductor fabrication process doesn't require a chemical-mechanical polishing process, so production costs are further lowered.
A conventional fabrication process of a via hole is shown by the cross-sectional diagrams in FIG. 1 through 1E. As referring to FIG. 1A, an IMD layer consisting of a HSQ layer 104 and an oxide layer 106 is formed on a substrate 100 having a pre-formed metal layer 102. The HSQ is first dissolved in a solvent to form a liquid-state dielectric, which is then sprayed on the substrate 100 in a spin coating process. A follow-up flow process planarizs the HSQ layer 104, and a curing process removes the solvent in order to harden the HSQ layer. The oxide layer 106 is formed by plasma-enhanced chemical vapor deposition.
Referring next to FIG. 1B, the oxide layer 106 and the HSQ 104 are patterned to form a via hole 110, and expose the metal layer 102 using a typical photolithography process. The photolithography process includes forming a patterned photoresist layer 108 on the oxide layer 106, and following this with an etching process, using the photoresist layer 108 as a etching mask to form the via hole 110.
Referring to FIG. 1C, the photoresist layer 108 is removed in an oxygen plasma ashing process. She polymer side products of the etching process are also removed by a liquid remover, such as
Referring to FIG. 1D, a metal layer 112, such as aluminum or tungsten, is formed on the substrate 100, wherein a typical process for forming, an aluminum layer is physical vapor deposition, and a typical process for forming a tungsten layer is chemical vapor deposition.
Next, referring to FIG. 1E, an etching back or a chemical-mechanical polishing process is performed to remove the metal layer 112 from the top of the oxide layer 106 to form a via 112a, electrically connected to the metal layer 102.
However, referring to FIG. 1C, the HSQ layer 104a exposed through the via hole 110 generates a hydrophilic bond, Si-OH, which absorbs moisture during the oxygen plasma etching process used to remove the photoresist layer 108. And, in the follow-up metal layer deposition, the moisture absorbed by the HSQ layer 104a generates an outgassing effect, which leads to the problem of via poisoning. According to the greatly increased integration of integrated circuits, an unlanded via is used to replace the conventional landed via for efficiently increasing the density of the devices. Any alignment errors in the phlotolithographic via hole patterning process result in an increase in the area of the HSQ layer 104a that is exposed, making the moisture absorbing, problem more serious.
On the other hand, the aspect ratio of the via hole 110 is increased in a highly integrated semiconductor device, and that causes poor step coverage on the metal layer 112. As shown in FIG. 2, the space 113 is caused by poor quality filling.